The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in a peripheral circuit region where the layout area can be decreased.
As semiconductor devices near high integration, high speed, low power consumption, and compact sizes, the design-rule for a MOSFET device under development has been continuously decreased. Accordingly, the size of a gate has been continuously decreased. This trend has decreased the size of a gate in a semiconductor device in a cell as well as in a peripheral circuit region. Particularly, the size of a gate in the peripheral circuit required by a 60 nm technology has been decreased to about 100 nm.
As a result, the existing planar transistor structure limits a threshold voltage (Vt) target of a MOSFET device that is required by a specific device.
There are many difficulties in forming a gate pattern. For example, the actual size of a gate used may be smaller than the target size resulting in a nonuniform gate profile where a gate layout is formed without a dummy gate.
Thus, in order to solve these difficulties, dummy gates having the same length and width as the actual gate are used when performing a gate layout. Such dummy gates are arranged with equal spaces as the actually used gate allowing for a true gate target for performing the gate layout.
FIG. 1 is a view illustrating a layout of a peripheral circuit region in accordance with the prior art. As shown, a circuit requiring high speed operation employs a structure where gate pads 130 and 140 are disposed at either end of the surface of the gate respectively and a bit line 150 that is connected to the gate pads 130 and 140 simultaneously to prevent variation of the turn-on speed of the gate when a gate 120 that is disposed on an active area 110 of a semiconductor substrate 100 is turned on.
In FIG. 1, reference symbols 160 and 170, which are not explained, denote metal wirings.
However, in the peripheral circuit region in accordance with the prior art, distances between the gates are not regular since the bit lines are disposed according to the spacing of a design-rule. As such, if the distances between the gates are not regular, it is difficult to pattern a gate in a photolithography process when performing a gate layout.
In order to solve the difficulty of gate patterning as described above, a dummy gate should be used when performing a gate layout. However, it is impossible to insert the dummy gate when performing a gate layout because the gate pads are disposed at both sides of the active area.
If the dummy gate is inserted when performing a gate layout, a space between the active areas in which the dummy gate is inserted is increased, which consequently results in an increase of a layout area of the device.